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<div class="header">
  <div class="summary">
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle">
<div class="title">Functions<div class="ingroups"><a class="el" href="group__group__sysclk.html">SysClk       (System Clock)</a> &raquo; <a class="el" href="group__group__sysclk__clk__slow.html">Slow Clock</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gab90aac1a92f5fa0256dce73097b8fc58"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__slow__funcs.html#gab90aac1a92f5fa0256dce73097b8fc58">Cy_SysClk_ClkSlowSetDivider</a> (uint8_t divider)</td></tr>
<tr class="memdesc:gab90aac1a92f5fa0256dce73097b8fc58"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the clock divider for the slow clock.  <a href="#gab90aac1a92f5fa0256dce73097b8fc58">More...</a><br /></td></tr>
<tr class="separator:gab90aac1a92f5fa0256dce73097b8fc58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb2d6633178611c2c0281939da363eac"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__slow__funcs.html#gabb2d6633178611c2c0281939da363eac">Cy_SysClk_ClkSlowGetDivider</a> (void)</td></tr>
<tr class="memdesc:gabb2d6633178611c2c0281939da363eac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reports the divider value for the slow clock.  <a href="#gabb2d6633178611c2c0281939da363eac">More...</a><br /></td></tr>
<tr class="separator:gabb2d6633178611c2c0281939da363eac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ca0c247dee5e69b25f173240db9ed53"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__clk__slow__funcs.html#ga7ca0c247dee5e69b25f173240db9ed53">Cy_SysClk_ClkSlowGetFrequency</a> (void)</td></tr>
<tr class="memdesc:ga7ca0c247dee5e69b25f173240db9ed53"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reports the frequency of the slow clock.  <a href="#ga7ca0c247dee5e69b25f173240db9ed53">More...</a><br /></td></tr>
<tr class="separator:ga7ca0c247dee5e69b25f173240db9ed53"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Function Documentation</h2>
<a id="gab90aac1a92f5fa0256dce73097b8fc58"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab90aac1a92f5fa0256dce73097b8fc58">&#9670;&nbsp;</a></span>Cy_SysClk_ClkSlowSetDivider()</h2>

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          <td class="memname">void Cy_SysClk_ClkSlowSetDivider </td>
          <td>(</td>
          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>divider</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Sets the clock divider for the slow clock. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">divider</td><td>Divider value between 0 and 255. Causes integer division of (divider value + 1), or division by 1 to 256.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>Call <a class="el" href="group__group__startup__config__system__functions.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a> after this function calling.</dd>
<dd>
This API is available for CAT1A &amp; CAT1C devices.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line">    <span class="comment">/* Scenario: HFCLK0 is configured and enabled. The Slow clock sourcing the</span></div><div class="line"><span class="comment">                 CM0+ core must run at a frequency that is 1/32 of HFCLK0. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Slow clock is sourced from Peri clock. Set the divider to 1 (freq = HFCLK0) */</span></div><div class="line">    <a class="code" href="group__group__sysclk__clk__peri__funcs.html#ga872a11532b18a5438e9bea423fc4076f">Cy_SysClk_ClkPeriSetDivider</a>(1u);</div><div class="line"></div><div class="line">    <span class="keywordflow">if</span>(32u != <a class="code" href="group__group__sysclk__clk__slow__funcs.html#gabb2d6633178611c2c0281939da363eac">Cy_SysClk_ClkSlowGetDivider</a>())</div><div class="line">    {</div><div class="line">        <a class="code" href="group__group__sysclk__clk__slow__funcs.html#gab90aac1a92f5fa0256dce73097b8fc58">Cy_SysClk_ClkSlowSetDivider</a>(32u);</div><div class="line">    }</div><div class="line"></div><div class="line">    <span class="comment">/* Get the CM0+ clock source frequency */</span></div><div class="line">    uint32_t clkSlowfreq = <a class="code" href="group__group__sysclk__clk__slow__funcs.html#ga7ca0c247dee5e69b25f173240db9ed53">Cy_SysClk_ClkSlowGetFrequency</a>();</div></div><!-- fragment --></dd></dl>

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<a id="gabb2d6633178611c2c0281939da363eac"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabb2d6633178611c2c0281939da363eac">&#9670;&nbsp;</a></span>Cy_SysClk_ClkSlowGetDivider()</h2>

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          <td class="memname">uint8_t Cy_SysClk_ClkSlowGetDivider </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reports the divider value for the slow clock. </p>
<dl class="section return"><dt>Returns</dt><dd>The divider value. The integer division done is by (divider value + 1), or division by 1 to 256.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This API is available for CAT1A &amp; CAT1C devices.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line">    <span class="comment">/* Scenario: HFCLK0 is configured and enabled. The Slow clock sourcing the</span></div><div class="line"><span class="comment">                 CM0+ core must run at a frequency that is 1/32 of HFCLK0. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Slow clock is sourced from Peri clock. Set the divider to 1 (freq = HFCLK0) */</span></div><div class="line">    <a class="code" href="group__group__sysclk__clk__peri__funcs.html#ga872a11532b18a5438e9bea423fc4076f">Cy_SysClk_ClkPeriSetDivider</a>(1u);</div><div class="line"></div><div class="line">    <span class="keywordflow">if</span>(32u != <a class="code" href="group__group__sysclk__clk__slow__funcs.html#gabb2d6633178611c2c0281939da363eac">Cy_SysClk_ClkSlowGetDivider</a>())</div><div class="line">    {</div><div class="line">        <a class="code" href="group__group__sysclk__clk__slow__funcs.html#gab90aac1a92f5fa0256dce73097b8fc58">Cy_SysClk_ClkSlowSetDivider</a>(32u);</div><div class="line">    }</div><div class="line"></div><div class="line">    <span class="comment">/* Get the CM0+ clock source frequency */</span></div><div class="line">    uint32_t clkSlowfreq = <a class="code" href="group__group__sysclk__clk__slow__funcs.html#ga7ca0c247dee5e69b25f173240db9ed53">Cy_SysClk_ClkSlowGetFrequency</a>();</div></div><!-- fragment --></dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga7ca0c247dee5e69b25f173240db9ed53">&#9670;&nbsp;</a></span>Cy_SysClk_ClkSlowGetFrequency()</h2>

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          <td class="memname">uint32_t Cy_SysClk_ClkSlowGetFrequency </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
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</div><div class="memdoc">

<p>Reports the frequency of the slow clock. </p>
<dl class="section return"><dt>Returns</dt><dd>The frequency, in Hz.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This API is available for CAT1A &amp; CAT1C devices.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line">    <span class="comment">/* Scenario: HFCLK0 is configured and enabled. The Slow clock sourcing the</span></div><div class="line"><span class="comment">                 CM0+ core must run at a frequency that is 1/32 of HFCLK0. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Slow clock is sourced from Peri clock. Set the divider to 1 (freq = HFCLK0) */</span></div><div class="line">    <a class="code" href="group__group__sysclk__clk__peri__funcs.html#ga872a11532b18a5438e9bea423fc4076f">Cy_SysClk_ClkPeriSetDivider</a>(1u);</div><div class="line"></div><div class="line">    <span class="keywordflow">if</span>(32u != <a class="code" href="group__group__sysclk__clk__slow__funcs.html#gabb2d6633178611c2c0281939da363eac">Cy_SysClk_ClkSlowGetDivider</a>())</div><div class="line">    {</div><div class="line">        <a class="code" href="group__group__sysclk__clk__slow__funcs.html#gab90aac1a92f5fa0256dce73097b8fc58">Cy_SysClk_ClkSlowSetDivider</a>(32u);</div><div class="line">    }</div><div class="line"></div><div class="line">    <span class="comment">/* Get the CM0+ clock source frequency */</span></div><div class="line">    uint32_t clkSlowfreq = <a class="code" href="group__group__sysclk__clk__slow__funcs.html#ga7ca0c247dee5e69b25f173240db9ed53">Cy_SysClk_ClkSlowGetFrequency</a>();</div></div><!-- fragment --></dd></dl>

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